switchtec.h

Go to the documentation of this file.

/*
 * Microsemi Switchtec(tm) PCIe Management Library
 * Copyright (c) 2017, Microsemi Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included
 * in all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
 
#ifndef LIBSWITCHTEC_SWITCHTEC_H
#define LIBSWITCHTEC_SWITCHTEC_H

 
#include "mrpc.h"
#include "bind.h"
#include "portable.h"
#include "registers.h"
#include "utils.h"
#include "inject.h"
 
#include <stdbool.h>
#include <stdlib.h>
#include <stdint.h>
#include <stdio.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
struct switchtec_dev;
 
#define SWITCHTEC_MAX_PARTS  48
#define SWITCHTEC_MAX_PORTS  60
#define SWITCHTEC_MAX_LANES  100
#define SWITCHTEC_MAX_STACKS 8
#define SWITCHTEC_PORTS_PER_STACK 8
#define SWITCHTEC_MAX_EVENT_COUNTERS 64
#define SWITCHTEC_UNBOUND_PORT 255
#define SWITCHTEC_PFF_PORT_VEP 100
 
#define SWITCHTEC_FLASH_BOOT_PART_START 0xa8000000
#define SWITCHTEC_FLASH_MAP0_PART_START 0xa8020000
#define SWITCHTEC_FLASH_MAP1_PART_START 0xa8040000
#define SWITCHTEC_FLASH_PART_LEN 0x10000
 
#define SWITCHTEC_CMD_MASK 0xffff
#define SWITCHTEC_PAX_ID_SHIFT 18
#define SWITCHTEC_PAX_ID_MASK 0x1f
#define SWITCHTEC_PAX_ID_LOCAL SWITCHTEC_PAX_ID_MASK
 
#define SWITCHTEC_DIAG_MAX_TLP_DWORDS 132
 
#define SWITCHTEC_MAX_GPIO_PIN_VALS 30
 
#ifdef __CHECKER__
#define __gas __attribute__((noderef, address_space(1)))
#else
#define __gas
#endif
 
#define _PURE __attribute__ ((pure))

typedef __gas struct switchtec_gas *gasptr_t;
#define SWITCHTEC_MAP_FAILED ((gasptr_t) -1)

enum switchtec_gen {
    SWITCHTEC_GEN3,
    SWITCHTEC_GEN4,
    SWITCHTEC_GEN5,
    SWITCHTEC_GEN_UNKNOWN,
};

enum switchtec_rev {
    SWITCHTEC_REVA = 0x0f,
    SWITCHTEC_REVB = 0x00,
    SWITCHTEC_REVC = 0x01,
    SWITCHTEC_REV_UNKNOWN = 0xff
};

enum switchtec_boot_phase {
    SWITCHTEC_BOOT_PHASE_BL1 = 1,
    SWITCHTEC_BOOT_PHASE_BL2,
    SWITCHTEC_BOOT_PHASE_FW,
    SWITCHTEC_BOOT_PHASE_UNKNOWN
};

enum switchtec_parition_types {
    SWITCHTEC_PART_TYPE_KEYMAN = 1,
    SWITCHTEC_PART_TYPE_RC = 2,
    SWITCHTEC_PART_TYPE_BL2 = 3,
    SWITCHTEC_PART_TYPE_CFG = 4,
    SWITCHTEC_PART_TYPE_FW = 5
};

enum switchtec_variant {
    SWITCHTEC_PFX,
    SWITCHTEC_PFXL,
    SWITCHTEC_PFXI,
    SWITCHTEC_PSX,
    SWITCHTEC_PAX,
    SWITCHTEC_PAXA,
    SWITCHTEC_PFXA,
    SWITCHTEC_PSXA,
    SWITCHTEC_VAR_UNKNOWN,
};

struct switchtec_device_info {
    char name[256];     
    char desc[256];     
    char pci_dev[256];  
    char product_id[32];    
    char product_rev[8];    
    char fw_version[32];    
    char path[PATH_MAX];    
};

struct switchtec_port_id {
    unsigned char partition;    
    unsigned char stack;        
    unsigned char upstream;     
    unsigned char stk_id;       
    unsigned char phys_id;      
    unsigned char log_id;       
};

struct switchtec_status {
    struct switchtec_port_id port;  
    unsigned char cfg_lnk_width;    
    unsigned char neg_lnk_width;    
    unsigned char link_up;      
    unsigned char link_rate;    
    uint16_t ltssm;         
    const char *ltssm_str;      
    unsigned char lane_reversal;    
    const char *lane_reversal_str;  
    unsigned char first_act_lane;   
    char lanes[17];
 
    char *pci_bdf;          
    char *pci_bdf_path;     
 
    char *pci_dev;          
    int vendor_id;          
    int device_id;          
    char *class_devices;        
    unsigned int acs_ctrl;      
};

enum switchtec_bw_type {
    SWITCHTEC_BW_TYPE_RAW = 0x0,
    SWITCHTEC_BW_TYPE_PAYLOAD = 0x1,
};

enum switchtec_log_type {
    SWITCHTEC_LOG_RAM,
    SWITCHTEC_LOG_FLASH,
    SWITCHTEC_LOG_FTDC,
    SWITCHTEC_LOG_MEMLOG,
    SWITCHTEC_LOG_REGS,
    SWITCHTEC_LOG_SYS_STACK,
    SWITCHTEC_LOG_THRD_STACK,
    SWITCHTEC_LOG_THRD,
    SWITCHTEC_LOG_NVHDR,
};

enum switchtec_log_parse_type {
    SWITCHTEC_LOG_PARSE_TYPE_APP,
    SWITCHTEC_LOG_PARSE_TYPE_MAILBOX,
    SWITCHTEC_LOG_PARSE_TYPE_FTDC
};

struct switchtec_log_file_info {
    unsigned int log_fw_version;
    unsigned int log_sdk_version;
    unsigned int def_fw_version;
    unsigned int def_sdk_version;
    bool version_mismatch;
    bool overflow;
    bool gen_unknown;
    bool gen_ignored;
};

enum switchtec_log_def_type {
    SWITCHTEC_LOG_DEF_TYPE_APP,
    SWITCHTEC_LOG_DEF_TYPE_MAILBOX
};
 
enum switchtec_fw_type {
    SWITCHTEC_FW_TYPE_UNKNOWN = 0,
    SWITCHTEC_FW_TYPE_BOOT,
    SWITCHTEC_FW_TYPE_MAP,
    SWITCHTEC_FW_TYPE_IMG,
    SWITCHTEC_FW_TYPE_CFG,
    SWITCHTEC_FW_TYPE_NVLOG,
    SWITCHTEC_FW_TYPE_SEEPROM,
    SWITCHTEC_FW_TYPE_KEY,
    SWITCHTEC_FW_TYPE_BL2,
    SWITCHTEC_FW_TYPE_RIOT,
};

struct switchtec_fw_image_info {
    enum switchtec_gen gen;         
    unsigned long part_id;          
    enum switchtec_fw_type type;        
    char version[32];           
    size_t part_addr;           
    size_t part_len;            
    size_t part_body_offset;        
    size_t image_len;           
    unsigned long image_crc;        
 
    bool valid;
    bool active;
    bool running;
    bool read_only;
 
    struct switchtec_fw_image_info *next;
    void *metadata;
 
    unsigned long secure_version;
    bool signed_image;
    uint8_t redundant;
};
 
struct switchtec_fw_part_summary {
    struct switchtec_fw_part_type {
        struct switchtec_fw_image_info *active, *inactive;
    } boot, map, img, cfg, nvlog, seeprom, key, bl2, riot;
 
    struct switchtec_fw_image_info *mult_cfg;
 
    int nr_info;
    struct switchtec_fw_image_info all[];
};

struct switchtec_event_summary {
    uint64_t global;    
    uint64_t part_bitmap;   
    unsigned local_part;    

    unsigned part[SWITCHTEC_MAX_PARTS];

    unsigned pff[SWITCHTEC_MAX_PFF_CSR];
};

enum switchtec_event_id {
    SWITCHTEC_EVT_INVALID = -1,
    SWITCHTEC_GLOBAL_EVT_STACK_ERROR,
    SWITCHTEC_GLOBAL_EVT_PPU_ERROR,
    SWITCHTEC_GLOBAL_EVT_ISP_ERROR,
    SWITCHTEC_GLOBAL_EVT_SYS_RESET,
    SWITCHTEC_GLOBAL_EVT_FW_EXC,
    SWITCHTEC_GLOBAL_EVT_FW_NMI,
    SWITCHTEC_GLOBAL_EVT_FW_NON_FATAL,
    SWITCHTEC_GLOBAL_EVT_FW_FATAL,
    SWITCHTEC_GLOBAL_EVT_TWI_MRPC_COMP,
    SWITCHTEC_GLOBAL_EVT_TWI_MRPC_COMP_ASYNC,
    SWITCHTEC_GLOBAL_EVT_CLI_MRPC_COMP,
    SWITCHTEC_GLOBAL_EVT_CLI_MRPC_COMP_ASYNC,
    SWITCHTEC_GLOBAL_EVT_GPIO_INT,
    SWITCHTEC_GLOBAL_EVT_GFMS,
    SWITCHTEC_PART_EVT_PART_RESET,
    SWITCHTEC_PART_EVT_MRPC_COMP,
    SWITCHTEC_PART_EVT_MRPC_COMP_ASYNC,
    SWITCHTEC_PART_EVT_DYN_PART_BIND_COMP,
    SWITCHTEC_PFF_EVT_AER_IN_P2P,
    SWITCHTEC_PFF_EVT_AER_IN_VEP,
    SWITCHTEC_PFF_EVT_DPC,
    SWITCHTEC_PFF_EVT_CTS,
    SWITCHTEC_PFF_EVT_UEC,
    SWITCHTEC_PFF_EVT_HOTPLUG,
    SWITCHTEC_PFF_EVT_IER,
    SWITCHTEC_PFF_EVT_THRESH,
    SWITCHTEC_PFF_EVT_POWER_MGMT,
    SWITCHTEC_PFF_EVT_TLP_THROTTLING,
    SWITCHTEC_PFF_EVT_FORCE_SPEED,
    SWITCHTEC_PFF_EVT_CREDIT_TIMEOUT,
    SWITCHTEC_PFF_EVT_LINK_STATE,
    SWITCHTEC_MAX_EVENTS,
};
 
/*********** Platform Functions ***********/
 
struct switchtec_dev *switchtec_open(const char *device);
struct switchtec_dev *switchtec_open_by_path(const char *path);
struct switchtec_dev *switchtec_open_by_index(int index);
struct switchtec_dev *switchtec_open_by_pci_addr(int domain, int bus,
                         int device, int func);
struct switchtec_dev *switchtec_open_i2c(const char *path, int i2c_addr);
struct switchtec_dev *switchtec_open_i2c_by_adapter(int adapter, int i2c_addr);
struct switchtec_dev *switchtec_open_uart(int fd);
struct switchtec_dev *switchtec_open_eth(const char *ip, const int inst);
 
void switchtec_close(struct switchtec_dev *dev);
int switchtec_list(struct switchtec_device_info **devlist);
void switchtec_list_free(struct switchtec_device_info *devlist);
int switchtec_get_fw_version(struct switchtec_dev *dev, char *buf,
                 size_t buflen);
int switchtec_get_device_version(struct switchtec_dev *dev, int *res);
int switchtec_cmd(struct switchtec_dev *dev, uint32_t cmd,
          const void *payload, size_t payload_len, void *resp,
          size_t resp_len);
int switchtec_get_devices(struct switchtec_dev *dev,
              struct switchtec_status *status,
              int ports);
int switchtec_pff_to_port(struct switchtec_dev *dev, int pff,
              int *partition, int *port);
int switchtec_port_to_pff(struct switchtec_dev *dev, int partition,
              int port, int *pff);
int switchtec_event_summary(struct switchtec_dev *dev,
                struct switchtec_event_summary *sum);
int switchtec_event_check(struct switchtec_dev *dev,
              struct switchtec_event_summary *check,
              struct switchtec_event_summary *res);
int switchtec_event_ctl(struct switchtec_dev *dev,
            enum switchtec_event_id e,
            int index, int flags,
            uint32_t data[5]);
int switchtec_event_wait(struct switchtec_dev *dev, int timeout_ms);
 
/*********** Generic Accessors ***********/
 
_PURE const char *switchtec_name(struct switchtec_dev *dev);
_PURE int switchtec_partition(struct switchtec_dev *dev);
_PURE int switchtec_device_id(struct switchtec_dev *dev);
_PURE enum switchtec_gen switchtec_gen(struct switchtec_dev *dev);
_PURE enum switchtec_variant switchtec_variant(struct switchtec_dev *dev);
_PURE enum switchtec_boot_phase
switchtec_boot_phase(struct switchtec_dev *dev);
int switchtec_set_pax_id(struct switchtec_dev *dev, int pax_id);
int switchtec_echo(struct switchtec_dev *dev, uint32_t input, uint32_t *output);
int switchtec_hard_reset(struct switchtec_dev *dev);
int switchtec_status(struct switchtec_dev *dev,
             struct switchtec_status **status);
void switchtec_status_free(struct switchtec_status *status, int ports);
int switchtec_get_device_info(struct switchtec_dev *dev,
                  enum switchtec_boot_phase *phase,
                  enum switchtec_gen *gen,
                  enum switchtec_rev *rev);
const char *switchtec_strerror(void);
void switchtec_perror(const char *str);
int switchtec_log_to_file(struct switchtec_dev *dev,
        enum switchtec_log_type type, int fd, FILE *log_def_file,
        struct switchtec_log_file_info *info);
int switchtec_parse_log(FILE *bin_log_file, FILE *log_def_file,
            FILE *parsed_log_file,
            enum switchtec_log_parse_type log_type,
            enum switchtec_gen gen,
            struct switchtec_log_file_info *info);
int switchtec_log_def_to_file(struct switchtec_dev *dev,
                  enum switchtec_log_def_type type,
                  FILE* file);
float switchtec_die_temp(struct switchtec_dev *dev);
int switchtec_die_temps(struct switchtec_dev *dev, int nr_sensor,
            float *sensor_readings);
int switchtec_calc_lane_id(struct switchtec_dev *dev, int phys_port_id,
               int lane_id, struct switchtec_status *port);
int switchtec_calc_port_lane(struct switchtec_dev *dev, int lane_id,
                 int *phys_port_id, int *port_lane_id,
                 struct switchtec_status *port);
int switchtec_calc_lane_mask(struct switchtec_dev *dev, int phys_port_id,
        int lane_id, int num_lanes, int *lane_mask,
        struct switchtec_status *port);

 
int switchtec_inject_err_dllp(struct switchtec_dev *dev, int phys_port_id,
                          int data);
int switchtec_inject_err_dllp_crc(struct switchtec_dev *dev, int phys_port_id,
                          int enable, uint16_t rate);
int switchtec_inject_err_tlp_lcrc(struct switchtec_dev *dev, int phys_port_id,
                          int enable, uint8_t rate);
int switchtec_inject_err_tlp_seq_num(struct switchtec_dev *dev, int phys_port_id);
int switchtec_inject_err_ack_nack(struct switchtec_dev *dev, int phys_port_id,
                          uint16_t seq_num, uint8_t count);
int switchtec_inject_err_cto(struct switchtec_dev *dev, int phys_port_id);

static inline int switchtec_is_gen3(struct switchtec_dev *dev)
{
    return switchtec_gen(dev) == SWITCHTEC_GEN3;
}

static inline int switchtec_is_gen4(struct switchtec_dev *dev)
{
    return switchtec_gen(dev) == SWITCHTEC_GEN4;
}

static inline int switchtec_is_gen5(struct switchtec_dev *dev)
{
    return switchtec_gen(dev) == SWITCHTEC_GEN5;
}

static inline int switchtec_max_supported_ports(struct switchtec_dev *dev)
{
    return switchtec_is_gen5(dev) ? SWITCHTEC_MAX_PORTS :
           switchtec_is_gen4(dev) ? 52 : 48;
}

static inline int switchtec_is_pfx(struct switchtec_dev *dev)
{
    return switchtec_variant(dev) == SWITCHTEC_PFX;
}

static inline int switchtec_is_pfxl(struct switchtec_dev *dev)
{
    return switchtec_variant(dev) == SWITCHTEC_PFXL;
}

static inline int switchtec_is_pfxi(struct switchtec_dev *dev)
{
    return switchtec_variant(dev) == SWITCHTEC_PFXI;
}

static inline int switchtec_is_pfxa(struct switchtec_dev *dev)
{
    return switchtec_variant(dev) == SWITCHTEC_PFXA;
}

static inline int switchtec_is_pfx_all(struct switchtec_dev *dev)
{
    return switchtec_is_pfx(dev) ||
           switchtec_is_pfxl(dev) ||
           switchtec_is_pfxi(dev) ||
           switchtec_is_pfxa(dev);
}

static inline int switchtec_is_psx(struct switchtec_dev *dev)
{
    return switchtec_variant(dev) == SWITCHTEC_PSX;
}

static inline int switchtec_is_psxa(struct switchtec_dev *dev)
{
    return switchtec_variant(dev) == SWITCHTEC_PSXA;
}

static inline int switchtec_is_psx_all(struct switchtec_dev *dev)
{
    return switchtec_is_psx(dev) ||
           switchtec_is_psxa(dev);
}

static inline int switchtec_is_psx_pfx_all(struct switchtec_dev *dev)
{
    return switchtec_is_psx_all(dev) || switchtec_is_pfx_all(dev);
}

static inline int switchtec_is_pax(struct switchtec_dev *dev)
{
    return switchtec_variant(dev) == SWITCHTEC_PAX;
}

static inline int switchtec_is_paxa(struct switchtec_dev *dev)
{
    return switchtec_variant(dev) == SWITCHTEC_PAXA;
}

static inline int switchtec_is_pax_all(struct switchtec_dev *dev)
{
    return switchtec_is_pax(dev) || switchtec_is_paxa(dev);
}

static inline const char *switchtec_gen_str(struct switchtec_dev *dev)
{
    const char *str;
 
    str =  switchtec_is_gen3(dev) ? "GEN3" :
           switchtec_is_gen4(dev) ? "GEN4" :
           switchtec_is_gen5(dev) ? "GEN5" : "Unknown";
 
    return str;
}

static inline const char *switchtec_rev_str(enum switchtec_rev rev)
{
    const char *str;
 
    str =  (rev == SWITCHTEC_REVA) ? "REVA" :
           (rev == SWITCHTEC_REVB) ? "REVB" :
           (rev == SWITCHTEC_REVC) ? "REVC" : "Unknown";
 
    return str;
}

static inline const char *
switchtec_fw_image_gen_str(struct switchtec_fw_image_info *inf)
{
    switch (inf->gen) {
    case SWITCHTEC_GEN3: return "GEN3";
    case SWITCHTEC_GEN4: return "GEN4";
    case SWITCHTEC_GEN5: return "GEN5";
    default:         return "UNKNOWN";
    }
}

static inline const char *switchtec_variant_str(struct switchtec_dev *dev)
{
    const char *str;
 
    str = switchtec_is_pfx(dev) ? "PFX" :
          switchtec_is_pfxl(dev) ? "PFX-L" :
          switchtec_is_pfxi(dev) ? "PFX-I" :
          switchtec_is_psx(dev) ? "PSX" :
          switchtec_is_pax(dev) ? "PAX" :
          switchtec_is_pfxa(dev) ? "PFX-A" :
          switchtec_is_psxa(dev) ? "PSX-A" :
          switchtec_is_paxa(dev) ? "PAX-A" : "Unknown";
 
    return str;
}

static inline const char* switchtec_phase_id_str(
        enum switchtec_boot_phase phase_id)
{
    switch(phase_id) {
    case SWITCHTEC_BOOT_PHASE_BL1:
        return "BL1";
    case SWITCHTEC_BOOT_PHASE_BL2:
        return "BL2";
    case SWITCHTEC_BOOT_PHASE_FW:
        return "Main Firmware";
    default:
        return "Unknown Phase";
    }
}

static const float switchtec_gen_transfers[] = {0, 2.5, 5, 8, 16, 32};
static const float switchtec_gen_datarate[] = {0, 250, 500, 985, 1969, 3938};
 
static inline const char *switchtec_ltssm_str_gen4(int ltssm, int show_minor)
{
    if (!show_minor)
        ltssm |= 0xFF00;
 
    switch(ltssm) {
    case 0x0000: return "Detect (INACTIVE)";
    case 0x0100: return "Detect (QUIET)";
    case 0x0200: return "Detect (SPD_CHD0)";
    case 0x0300: return "Detect (SPD_CHD1)";
    case 0x0400: return "Detect (ACTIVE0)";
    case 0x0500: return "Detect (ACTIVE1)";
    case 0x0600: return "Detect (P1_TO_P0)";
    case 0x0700: return "Detect (P0_TO_P1_0)";
    case 0x0800: return "Detect (P0_TO_P1_1)";
    case 0x0900: return "Detect (P0_TO_P1_2)";
    case 0xFF00: return "Detect";
    case 0x0001: return "Polling (INACTIVE)";
    case 0x0101: return "Polling (ACTIVE_ENTRY)";
    case 0x0201: return "Polling (ACTIVE)";
    case 0x0301: return "Polling (CFG)";
    case 0x0401: return "Polling (COMP)";
    case 0x0501: return "Polling (COMP_ENTRY)";
    case 0x0601: return "Polling (COMP_EIOS)";
    case 0x0701: return "Polling (COMP_EIOS_ACK)";
    case 0x0801: return "Polling (COMP_IDLE)";
    case 0xFF01: return "Polling";
    case 0x0002: return "Config (INACTIVE)";
    case 0x0102: return "Config (US_LW_START)";
    case 0x0202: return "Config (US_LW_ACCEPT)";
    case 0x0302: return "Config (US_LN_WAIT)";
    case 0x0402: return "Config (US_LN_ACCEPT)";
    case 0x0502: return "Config (DS_LW_START)";
    case 0x0602: return "Config (DS_LW_ACCEPT)";
    case 0x0702: return "Config (DS_LN_WAIT)";
    case 0x0802: return "Config (DS_LN_ACCEPT)";
    case 0x0902: return "Config (COMPLETE)";
    case 0x0A02: return "Config (IDLE)";
    case 0xFF02: return "Config";
    case 0x0003: return "L0 (INACTIVE)";
    case 0x0103: return "L0 (L0)";
    case 0x0203: return "L0 (TX_EL_IDLE)";
    case 0x0303: return "L0 (TX_IDLE_MIN)";
    case 0xFF03: return "L0";
    case 0x0004: return "Recovery (INACTIVE)";
    case 0x0104: return "Recovery (RCVR_LOCK)";
    case 0x0204: return "Recovery (RCVR_CFG)";
    case 0x0304: return "Recovery (IDLE)";
    case 0x0404: return "Recovery (SPEED0)";
    case 0x0504: return "Recovery (SPEED1)";
    case 0x0604: return "Recovery (SPEED2)";
    case 0x0704: return "Recovery (SPEED3)";
    case 0x0804: return "Recovery (EQ_PH0)";
    case 0x0904: return "Recovery (EQ_PH1)";
    case 0x0A04: return "Recovery (EQ_PH2)";
    case 0x0B04: return "Recovery (EQ_PH3)";
    case 0xFF04: return "Recovery";
    case 0x0005: return "Disable (INACTIVE)";
    case 0x0105: return "Disable (DISABLE0)";
    case 0x0205: return "Disable (DISABLE1)";
    case 0x0305: return "Disable (DISABLE2)";
    case 0x0405: return "Disable (DISABLE3)";
    case 0xFF05: return "Disable";
    case 0x0006: return "Loop Back (INACTIVE)";
    case 0x0106: return "Loop Back (ENTRY)";
    case 0x0206: return "Loop Back (ENTRY_EXIT)";
    case 0x0306: return "Loop Back (EIOS)";
    case 0x0406: return "Loop Back (EIOS_ACK)";
    case 0x0506: return "Loop Back (IDLE)";
    case 0x0606: return "Loop Back (ACTIVE)";
    case 0x0706: return "Loop Back (EXIT0)";
    case 0x0806: return "Loop Back (EXIT1)";
    case 0xFF06: return "Loop Back";
    case 0x0007: return "Hot Reset (INACTIVE)";
    case 0x0107: return "Hot Reset (HOT_RESET)";
    case 0x0207: return "Hot Reset (MASTER_UP)";
    case 0x0307: return "Hot Reset (MASTER_DOWN)";
    case 0xFF07: return "Hot Reset";
    case 0x0008: return "TxL0s (INACTIVE)";
    case 0x0108: return "TxL0s (IDLE)";
    case 0x0208: return "TxL0s (T0_L0)";
    case 0x0308: return "TxL0s (FTS0)";
    case 0x0408: return "TxL0s (FTS1)";
    case 0xFF08: return "TxL0s";
    case 0x0009: return "L1 (INACTIVE)";
    case 0x0109: return "L1 (IDLE)";
    case 0x0209: return "L1 (SUBSTATE)";
    case 0x0309: return "L1 (SPD_CHG1)";
    case 0x0409: return "L1 (T0_L0)";
    case 0xFF09: return "L1";
    case 0x000A: return "L2 (INACTIVE)";
    case 0x010A: return "L2 (IDLE)";
    case 0x020A: return "L2 (TX_WAKE0)";
    case 0x030A: return "L2 (TX_WAKE1)";
    case 0x040A: return "L2 (EXIT)";
    case 0x050A: return "L2 (SPEED)";
    case 0xFF0A: return "L2";
    default: return "UNKNOWN";
    }
 
}
 
static inline const char *switchtec_ltssm_str_gen5(int ltssm, int show_minor)
{
    if (!show_minor)
        ltssm |= 0xFF00;
 
    switch(ltssm) {
    case 0x0000: return "Detect (INACTIVE)";
    case 0x0100: return "Detect (QUIET)";
    case 0x0200: return "Detect (SPD_CHG0)";
    case 0x0300: return "Detect (SPD_CHG1)";
    case 0x0400: return "Detect (ACTIVE0)";
    case 0x0500: return "Detect (ACTIVE1)";
    case 0x0600: return "Detect (ACTIVE2)";
    case 0x0700: return "Detect (P1_TO_P0)";
    case 0x0800: return "Detect (P0_TO_P1_0)";
    case 0x0900: return "Detect (P0_TO_P1_1)";
    case 0x0A00: return "Detect (P0_TO_P1_2)";
    case 0xFF00: return "Detect";
    case 0x0001: return "Polling (INACTIVE)";
    case 0x0101: return "Polling (ACTIVE_ENTRY)";
    case 0x0201: return "Polling (ACTIVE)";
    case 0x0301: return "Polling (CFG)";
    case 0x0401: return "Polling (COMP)";
    case 0x0501: return "Polling (COMP_ENTRY)";
    case 0x0601: return "Polling (COMP_EIOS)";
    case 0x0701: return "Polling (COMP_EIOS_ACK)";
    case 0x0801: return "Polling (COMP_IDLE)";
    case 0xFF01: return "Polling";
    case 0x0002: return "Config (INACTIVE)";
    case 0x0102: return "Config (US_LW_START)";
    case 0x0202: return "Config (US_LW_ACCEPT)";
    case 0x0302: return "Config (US_LN_WAIT)";
    case 0x0402: return "Config (US_LN_ACCEPT)";
    case 0x0502: return "Config (DS_LW_START)";
    case 0x0602: return "Config (DS_LW_ACCEPT)";
    case 0x0702: return "Config (DS_LN_WAIT)";
    case 0x0802: return "Config (DS_LN_ACCEPT)";
    case 0x0902: return "Config (COMPLETE)";
    case 0x0A02: return "Config (IDLE)";
    case 0xFF02: return "Config";
    case 0x0003: return "L0 (INACTIVE)";
    case 0x0103: return "L0 (L0)";
    case 0x0203: return "L0 (TX_EL_IDLE)";
    case 0x0303: return "L0 (TX_IDLE_MIN)";
    case 0xFF03: return "L0";
    case 0x0004: return "Recovery (INACTIVE)";
    case 0x0104: return "Recovery (RCVR_LOCK)";
    case 0x0204: return "Recovery (RCVR_CFG)";
    case 0x0304: return "Recovery (IDLE)";
    case 0x0404: return "Recovery (SPEED0)";
    case 0x0504: return "Recovery (SPEED1)";
    case 0x0604: return "Recovery (SPEED2)";
    case 0x0704: return "Recovery (SPEED3)";
    case 0x0804: return "Recovery (EQ_PH0)";
    case 0x0904: return "Recovery (EQ_PH1)";
    case 0x0A04: return "Recovery (EQ_PH2)";
    case 0x0B04: return "Recovery (EQ_PH3)";
    case 0xFF04: return "Recovery";
    case 0x0005: return "Disable (INACTIVE)";
    case 0x0105: return "Disable (DISABLE0)";
    case 0x0205: return "Disable (DISABLE1)";
    case 0x0305: return "Disable (DISABLE2)";
    case 0x0405: return "Disable (DISABLE3)";
    case 0xFF05: return "Disable";
    case 0x0006: return "Loop Back (INACTIVE)";
    case 0x0106: return "Loop Back (ENTRY)";
    case 0x0206: return "Loop Back (ENTRY_EXIT)";
    case 0x0306: return "Loop Back (EIOS)";
    case 0x0406: return "Loop Back (EIOS_ACK)";
    case 0x0506: return "Loop Back (IDLE)";
    case 0x0606: return "Loop Back (ACTIVE)";
    case 0x0706: return "Loop Back (EXIT0)";
    case 0x0806: return "Loop Back (EXIT1)";
    case 0xFF06: return "Loop Back";
    case 0x0007: return "Hot Reset (INACTIVE)";
    case 0x0107: return "Hot Reset (HOT_RESET)";
    case 0x0207: return "Hot Reset (MASTER_UP)";
    case 0x0307: return "Hot Reset (MASTER_DOWN)";
    case 0xFF07: return "Hot Reset";
    case 0x0008: return "TxL0s (INACTIVE)";
    case 0x0108: return "TxL0s (IDLE)";
    case 0x0208: return "TxL0s (T0_L0)";
    case 0x0308: return "TxL0s (FTS0)";
    case 0x0408: return "TxL0s (FTS1)";
    case 0xFF08: return "TxL0s";
    case 0x0009: return "L1 (INACTIVE)";
    case 0x0109: return "L1 (IDLE)";
    case 0x0209: return "L1 (SUBSTATE)";
    case 0x0309: return "L1 (TO_L0)";
    case 0xFF09: return "L1";
    case 0x000A: return "L2 (INACTIVE)";
    case 0x010A: return "L2 (IDLE)";
    case 0x020A: return "L2 (TX_WAKE0)";
    case 0x030A: return "L2 (TX_WAKE1)";
    case 0x040A: return "L2 (EXIT)";
    case 0x050A: return "L2 (SPEED)";
    case 0xFF0A: return "L2";
    default: return "UNKNOWN";
    }
}
 
static inline const char *switchtec_ltssm_str(int ltssm, int show_minor,
                          struct switchtec_dev *dev)
{
    if(switchtec_is_gen5(dev))
        return switchtec_ltssm_str_gen5(ltssm, show_minor);
    else
        return switchtec_ltssm_str_gen4(ltssm, show_minor);
}
 
/*********** EVENT Handling ***********/

enum switchtec_event_flags {
    SWITCHTEC_EVT_FLAG_CLEAR = 1 << 0,
    SWITCHTEC_EVT_FLAG_EN_POLL = 1 << 1,
    SWITCHTEC_EVT_FLAG_EN_LOG = 1 << 2,
    SWITCHTEC_EVT_FLAG_EN_CLI = 1 << 3,
    SWITCHTEC_EVT_FLAG_EN_FATAL = 1 << 4,
    SWITCHTEC_EVT_FLAG_DIS_POLL = 1 << 5,
    SWITCHTEC_EVT_FLAG_DIS_LOG = 1 << 6,
    SWITCHTEC_EVT_FLAG_DIS_CLI = 1 << 7,
    SWITCHTEC_EVT_FLAG_DIS_FATAL = 1 << 8,
};

enum switchtec_event_special {
    SWITCHTEC_EVT_IDX_LOCAL = -1,
    SWITCHTEC_EVT_IDX_ALL = -2,
};

enum switchtec_event_type {
    SWITCHTEC_EVT_GLOBAL,
    SWITCHTEC_EVT_PART,
    SWITCHTEC_EVT_PFF,
};
 
int switchtec_event_summary_set(struct switchtec_event_summary *sum,
                enum switchtec_event_id e,
                int index);
int switchtec_event_summary_test(struct switchtec_event_summary *sum,
                 enum switchtec_event_id e,
                 int index);
int switchtec_event_summary_iter(struct switchtec_event_summary *sum,
                 enum switchtec_event_id *e,
                 int *idx);
enum switchtec_event_type switchtec_event_info(enum switchtec_event_id e,
                           const char **name,
                           const char **desc);
int switchtec_event_wait_for(struct switchtec_dev *dev,
                 enum switchtec_event_id e, int index,
                 struct switchtec_event_summary *res,
                 int timeout_ms);
 
/******** FIRMWARE Management ********/

enum switchtec_fw_dlstatus {
    SWITCHTEC_DLSTAT_READY = 0x0,
    SWITCHTEC_DLSTAT_INPROGRESS = 0x1,
    SWITCHTEC_DLSTAT_HEADER_INCORRECT = 0x2,
    SWITCHTEC_DLSTAT_OFFSET_INCORRECT = 0x3,
    SWITCHTEC_DLSTAT_CRC_INCORRECT = 0x4,
    SWITCHTEC_DLSTAT_LENGTH_INCORRECT = 0x5,
    SWITCHTEC_DLSTAT_HARDWARE_ERR = 0x6,
    SWITCHTEC_DLSTAT_COMPLETES = 0x7,
    SWITCHTEC_DLSTAT_SUCCESS_FIRM_ACT = 0x8,
    SWITCHTEC_DLSTAT_SUCCESS_DATA_ACT = 0x9,
    SWITCHTEC_DLSTAT_PACKAGE_TOO_SMALL = 0xa,
    SWITCHTEC_DLSTAT_SIG_MEM_ALLOC = 0xb,
    SWITCHTEC_DLSTAT_SEEPROM = 0xc,
    SWITCHTEC_DLSTAT_READONLY_PARTITION = 0xd,
    SWITCHTEC_DLSTAT_DOWNLOAD_TIMEOUT = 0xe,
    SWITCHTEC_DLSTAT_SEEPROM_TWI_NOT_ENABLED = 0xf,
    SWITCHTEC_DLSTAT_PROGRAM_RUNNING = 0x10,
    SWITCHTEC_DLSTAT_NOT_ALLOWED = 0x11,
    SWITCHTEC_DLSTAT_XML_MISMATCH_ACT = 0x12,
    SWITCHTEC_DLSTAT_UNKNOWN_ACT = 0x13,
 
    SWITCHTEC_DLSTAT_ERROR_PROGRAM = 0x1000,
    SWITCHTEC_DLSTAT_ERROR_OFFSET = 0x1001,
 
    SWITCHTEC_DLSTAT_NO_FILE = 0x7d009,
};

enum switchtec_fw_ro {
    SWITCHTEC_FW_RW = 0,
    SWITCHTEC_FW_RO = 1,
};
 
int switchtec_fw_set_redundant_flag(struct switchtec_dev *dev, 
                    int keyman, int riot, 
                    int bl2, int cfg, int fw, 
                    int set);
int switchtec_fw_toggle_active_partition(struct switchtec_dev *dev,
                     int toggle_bl2, int toggle_key,
                     int toggle_fw, int toggle_cfg,
                     int toggle_riotcore);
int switchtec_fw_write_fd(struct switchtec_dev *dev, int img_fd,
              int dont_activate, int force,
              void (*progress_callback)(int cur, int tot));
int switchtec_fw_write_file(struct switchtec_dev *dev, FILE *fimg,
                int dont_activate, int force,
                void (*progress_callback)(int cur, int tot));
int switchtec_fw_read_fd(struct switchtec_dev *dev, int fd,
             unsigned long addr, size_t len,
             void (*progress_callback)(int cur, int tot));
int switchtec_fw_body_read_fd(struct switchtec_dev *dev, int fd,
                  struct switchtec_fw_image_info *info,
                  void (*progress_callback)(int cur, int tot));
int switchtec_fw_read(struct switchtec_dev *dev, unsigned long addr,
              size_t len, void *buf);
void switchtec_fw_perror(const char *s, int ret);
int switchtec_fw_file_info(int fd, struct switchtec_fw_image_info *info);
int switchtec_get_device_id_bl2(struct switchtec_dev *dev,
                unsigned short *device_id);
int switchtec_fw_file_secure_version_newer(struct switchtec_dev *dev,
                       int img_fd);
const char *switchtec_fw_image_type(const struct switchtec_fw_image_info *info);
struct switchtec_fw_part_summary *
switchtec_fw_part_summary(struct switchtec_dev *dev);
void switchtec_fw_part_summary_free(struct switchtec_fw_part_summary *summary);
int switchtec_fw_img_write_hdr(int fd, struct switchtec_fw_image_info *info);
int switchtec_fw_is_boot_ro(struct switchtec_dev *dev);
int switchtec_fw_set_boot_ro(struct switchtec_dev *dev,
                 enum switchtec_fw_ro ro);
enum switchtec_gen switchtec_fw_version_to_gen(unsigned int version);
int switchtec_bind_info(struct switchtec_dev *dev,
            struct switchtec_bind_status_out *bind_status,
            int phy_port);
int switchtec_bind(struct switchtec_dev *dev, int par_id,
           int log_port, int phy_port);
int switchtec_unbind(struct switchtec_dev *dev, int par_id, int log_port);
bool switchtec_stack_bif_port_valid(struct switchtec_dev *dev, int stack_id,
                    int port_id);
int switchtec_stack_bif_width(struct switchtec_dev *dev, int stack_id,
                  int port_bif);
int switchtec_get_stack_bif(struct switchtec_dev *dev, int stack_id,
                int port_bif[SWITCHTEC_PORTS_PER_STACK]);
int switchtec_set_stack_bif(struct switchtec_dev *dev, int stack_id,
                int port_bif[SWITCHTEC_PORTS_PER_STACK]);
 
/******** GPIO Management ********/
 
struct switchtec_gpio {
    uint8_t sub_cmd;
    uint8_t resvd;
    uint16_t log_gpio_id;
    uint8_t data;
    uint8_t resvd1[3];
};
 
struct switchtec_gpio_sts_out {
    uint8_t sub_cmd;
    uint8_t resvd;
    uint16_t pin_num;
    uint32_t pin_values[SWITCHTEC_MAX_GPIO_PIN_VALS];
};
 
int switchtec_get_gpio(struct switchtec_dev *dev, int pin_id,
               int *gpio_val);
int switchtec_set_gpio(struct switchtec_dev *dev, int pin_id,
               int gpio_val);
int switchtec_get_gpio_direction_cfg(struct switchtec_dev *dev, int pin_id,
                     int *direction);
int switchtec_get_gpio_polarity_cfg(struct switchtec_dev *dev, int pin_id,
                    int *polarity);
int switchtec_en_dis_interrupt(struct switchtec_dev *dev, int pin_id, int en);
int switchtec_get_all_pin_sts(struct switchtec_dev *dev, uint32_t *values);
 
/********** EVENT COUNTER *********/

enum switchtec_evcntr_type_mask {
    UNSUP_REQ_ERR = 1 << 0,     
    ECRC_ERR = 1 << 1,      
    MALFORM_TLP_ERR = 1 << 2,   
    RCVR_OFLOW_ERR = 1 << 3,    
    CMPLTR_ABORT_ERR = 1 << 4,  
    POISONED_TLP_ERR = 1 << 5,  
    SURPRISE_DOWN_ERR = 1 << 6, 
    DATA_LINK_PROTO_ERR = 1 << 7,   
    HDR_LOG_OFLOW_ERR = 1 << 8, 
    UNCOR_INT_ERR = 1 << 9,     
    REPLAY_TMR_TIMEOUT = 1 << 10,   
    REPLAY_NUM_ROLLOVER = 1 << 11,  
    BAD_DLLP = 1 << 12,     
    BAD_TLP = 1 << 13,      
    RCVR_ERR = 1 << 14,     
    RCV_FATAL_MSG = 1 << 15,    
    RCV_NON_FATAL_MSG = 1 << 16,    
    RCV_CORR_MSG = 1 << 17,     
    NAK_RCVD = 1 << 18,     
    RULE_TABLE_HIT = 1 << 19,   
    POSTED_TLP = 1 << 20,       
    COMP_TLP = 1 << 21,     
    NON_POSTED_TLP = 1 << 22,   

    ALL_ERRORS = (UNSUP_REQ_ERR | ECRC_ERR | MALFORM_TLP_ERR |
              RCVR_OFLOW_ERR | CMPLTR_ABORT_ERR | POISONED_TLP_ERR |
              SURPRISE_DOWN_ERR | DATA_LINK_PROTO_ERR |
              HDR_LOG_OFLOW_ERR | UNCOR_INT_ERR |
              REPLAY_TMR_TIMEOUT | REPLAY_NUM_ROLLOVER |
              BAD_DLLP | BAD_TLP | RCVR_ERR | RCV_FATAL_MSG |
              RCV_NON_FATAL_MSG | RCV_CORR_MSG | NAK_RCVD),
    ALL_TLPS = (POSTED_TLP | COMP_TLP | NON_POSTED_TLP),

    ALL = (1 << 23) - 1,
};

extern const struct switchtec_evcntr_type_list {
    enum switchtec_evcntr_type_mask mask;
    const char *name;
    const char *help;
} switchtec_evcntr_type_list[];

struct switchtec_evcntr_setup {
    unsigned port_mask; //<! Mask of ports this counter counts

    enum switchtec_evcntr_type_mask type_mask;
    int egress;     //<! If 1, count egress, otherwise on ingress

    unsigned threshold;
};
 
int switchtec_evcntr_type_count(void);
const char *switchtec_evcntr_type_str(int *type_mask);
int switchtec_evcntr_setup(struct switchtec_dev *dev, unsigned stack_id,
               unsigned cntr_id,
               struct switchtec_evcntr_setup *setup);
int switchtec_evcntr_get_setup(struct switchtec_dev *dev, unsigned stack_id,
                   unsigned cntr_id, unsigned nr_cntrs,
                   struct switchtec_evcntr_setup *res);
int switchtec_evcntr_get(struct switchtec_dev *dev, unsigned stack_id,
             unsigned cntr_id, unsigned nr_cntrs, unsigned *res,
             int clear);
int switchtec_evcntr_get_both(struct switchtec_dev *dev, unsigned stack_id,
                  unsigned cntr_id, unsigned nr_cntrs,
                  struct switchtec_evcntr_setup *setup,
                  unsigned *counts, int clear);
int switchtec_evcntr_wait(struct switchtec_dev *dev, int timeout_ms);
 
/********** BANDWIDTH COUNTER *********/

struct switchtec_bwcntr_res {
    uint64_t time_us;       
    struct switchtec_bwcntr_dir {
        uint64_t posted;    
        uint64_t comp;      
        uint64_t nonposted; 
    } egress,           
      ingress;          
};
 
void switchtec_bwcntr_sub(struct switchtec_bwcntr_res *new_cntr,
              struct switchtec_bwcntr_res *old_cntr);
int switchtec_bwcntr_set_many(struct switchtec_dev *dev, int nr_ports,
                  int * phys_port_ids,
                  enum switchtec_bw_type bw_type);
int switchtec_bwcntr_set_all(struct switchtec_dev *dev,
                 enum switchtec_bw_type bw_type);
int switchtec_bwcntr_many(struct switchtec_dev *dev, int nr_ports,
              int *phys_port_ids, int clear,
              struct switchtec_bwcntr_res *res);
int switchtec_bwcntr_all(struct switchtec_dev *dev, int clear,
             struct switchtec_port_id **ports,
             struct switchtec_bwcntr_res **res);
uint64_t switchtec_bwcntr_tot(struct switchtec_bwcntr_dir *d);
 
/********** LATENCY COUNTER *********/
 
#define SWITCHTEC_LAT_ALL_INGRESS 63
 
int switchtec_lat_setup_many(struct switchtec_dev *dev, int nr_ports,
                 int *egress_port_ids, int *ingress_port_ids);
int switchtec_lat_setup(struct switchtec_dev *dev, int egress_port_id,
            int ingress_port_id, int clear);
int switchtec_lat_get_many(struct switchtec_dev *dev, int nr_ports,
               int clear, int *egress_port_ids,
               int *cur_ns, int *max_ns);
int switchtec_lat_get(struct switchtec_dev *dev, int clear,
              int egress_port_ids, int *cur_ns,
              int *max_ns);
 
/********** GLOBAL ADDRESS SPACE ACCESS *********/
 
/*
 * GAS map maps the hardware registers into user memory space.
 * Needless to say, this can be very dangerous and should only
 * be done if you know what you are doing. Any register accesses
 * that use this will remain unsupported by Microsemi unless it's
 * done within the switchtec user project or otherwise specified.
 */
 
gasptr_t switchtec_gas_map(struct switchtec_dev *dev, int writeable,
                           size_t *map_size);
void switchtec_gas_unmap(struct switchtec_dev *dev, gasptr_t map);
 
/********** DIAGNOSTIC FUNCTIONS *********/
 
#define SWITCHTEC_DIAG_CROSS_HAIR_ALL_LANES -1
#define SWITCHTEC_DIAG_CROSS_HAIR_MAX_LANES 64
 
enum switchtec_diag_cross_hair_state {
    SWITCHTEC_DIAG_CROSS_HAIR_DISABLED = 0,
    SWITCHTEC_DIAG_CROSS_HAIR_RESVD,
    SWITCHTEC_DIAG_CROSS_HAIR_WAITING,
    SWITCHTEC_DIAG_CROSS_HAIR_FIRST_ERROR_RIGHT,
    SWITCHTEC_DIAG_CROSS_HAIR_ERROR_FREE_RIGHT,
    SWITCHTEC_DIAG_CROSS_HAIR_FINAL_RIGHT,
    SWITCHTEC_DIAG_CROSS_HAIR_FIRST_ERROR_LEFT,
    SWITCHTEC_DIAG_CROSS_HAIR_ERROR_FREE_LEFT,
    SWITCHTEC_DIAG_CROSS_HAIR_FINAL_LEFT,
    SWITCHTEC_DIAG_CROSS_HAIR_FIRST_ERROR_TOP_RIGHT,
    SWITCHTEC_DIAG_CROSS_HAIR_ERROR_FREE_TOP_RIGHT,
    SWITCHTEC_DIAG_CROSS_HAIR_FINAL_TOP_RIGHT,
    SWITCHTEC_DIAG_CROSS_HAIR_FIRST_ERROR_BOT_RIGHT,
    SWITCHTEC_DIAG_CROSS_HAIR_ERROR_FREE_BOT_RIGHT,
    SWITCHTEC_DIAG_CROSS_HAIR_FINAL_BOT_RIGHT,
    SWITCHTEC_DIAG_CROSS_HAIR_FIRST_ERROR_TOP_LEFT,
    SWITCHTEC_DIAG_CROSS_HAIR_ERROR_FREE_TOP_LEFT,
    SWITCHTEC_DIAG_CROSS_HAIR_FINAL_TOP_LEFT,
    SWITCHTEC_DIAG_CROSS_HAIR_FIRST_ERROR_BOT_LEFT,
    SWITCHTEC_DIAG_CROSS_HAIR_ERROR_FREE_BOT_LEFT,
    SWITCHTEC_DIAG_CROSS_HAIR_FINAL_BOT_LEFT,
    SWITCHTEC_DIAG_CROSS_HAIR_DONE,
    SWITCHTEC_DIAG_CROSS_HAIR_ERROR,
};
 
struct switchtec_diag_cross_hair {
    enum switchtec_diag_cross_hair_state state;
    int lane_id;
 
    union {
        struct {
            /* Valid when state is Error */
            int prev_state;
            int x_pos;
            int y_pos;
        };
        /* Valid when state is DONE */
        struct {
            int eye_left_lim;
            int eye_right_lim;
            int eye_bot_left_lim;
            int eye_bot_right_lim;
            int eye_top_left_lim;
            int eye_top_right_lim;
        };
    };
};
 
struct switchtec_rcvr_obj {
    int port_id;
    int lane_id;
    int ctle;
    int target_amplitude;
    int speculative_dfe;
    int dynamic_dfe[7];
};
 
struct switchtec_port_eq_coeff {
    uint8_t lane_cnt;
    uint8_t reserved[3];
    struct {
        uint8_t pre;
        uint8_t post;
    } cursors[16];
};
 
struct switchtec_rem_port_eq_coeff {
    uint8_t lane_cnt;
    uint8_t reserved[3];
    struct {
        uint8_t is_coef;
        uint8_t pre;
        uint8_t post;
        uint8_t preset;
    } cursors[16];
};
 
enum lane_eq_dump_type_enum {
    LANE_EQ_DUMP_TYPE_CURR,   
    LANE_EQ_DUMP_TYPE_PREV,   
    LANE_EQ_DUMP_TYPE_NUM     
};
 
enum link_rate_enum {
    PCIE_LINK_RATE_INV  = 0,  
    PCIE_LINK_RATE_GEN1 = 1,  
    PCIE_LINK_RATE_GEN2 = 2,  
    PCIE_LINK_RATE_GEN3 = 3,  
    PCIE_LINK_RATE_GEN4 = 4,  
    PCIE_LINK_RATE_GEN5 = 5,  
    PCIE_LINK_RATE_NUM  = 5   
};
 
struct switchtec_port_eq_coeff_in {
    uint8_t cmd;
    uint8_t op_type;
    uint8_t phys_port_id;
    uint8_t lane_id;
    uint8_t dump_type;
    uint8_t prev_rate;
    uint8_t reserved[2];
};
 
struct switchtec_port_eq_table_in {
    uint8_t sub_cmd;
    uint8_t port_id;
    uint8_t dump_type;
    uint8_t prev_rate;
};
 
struct switchtec_port_eq_table {
    int lane_id;
    int step_cnt;
 
    struct {
        int pre_cursor;
        int post_cursor;
        int fom;
        int pre_cursor_up;
        int post_cursor_up;
        int error_status;
        int active_status;
        int speed;
    } steps[126];
};
 
struct switchtec_gen5_port_eq_table {
    uint8_t lane_id;
    uint8_t step_cnt;
    uint8_t reserved[2];
 
    struct {
        uint8_t pre_cursor;
        uint8_t post_cursor;
        uint16_t reserved_0;
        uint8_t reserved_1;
        uint8_t error_status;
        uint8_t active_status;
        uint8_t speed;
    } steps[25];
};
 
struct switchtec_port_eq_tx_fslf {
    int fs;
    int lf;
};
 
struct switchtec_port_eq_tx_fslf_out {
    uint8_t fs;
    uint8_t lf;
    uint8_t reserved[2];
};
 
struct switchtec_port_eq_tx_fslf_in {
    uint8_t sub_cmd;
    uint8_t port_id;
    uint8_t lane_id;
    uint8_t dump_type;
    uint8_t prev_rate;
    uint8_t reserved[3];
};
 
struct switchtec_rcvr_ext {
    int ctle2_rx_mode;
    int dtclk_5;
    int dtclk_8_6;
    int dtclk_9;
};
 
struct switchtec_mrpc {
    const char *tag;
    const char *desc;
    bool reserved;
};
 
enum switchtec_diag_eye_data_mode {
    SWITCHTEC_DIAG_EYE_RAW,
    SWITCHTEC_DIAG_EYE_RATIO,
};
 
struct switchtec_gen5_diag_eye_status_in {
    uint8_t sub_cmd;
    uint8_t resvd1[3];
};
 
struct switchtec_gen5_diag_eye_status_out {
    uint8_t status;
    uint8_t resvd1[3];
};
 
struct switchtec_gen5_diag_eye_read_in {
    uint8_t sub_cmd;
    uint8_t lane_id;
    uint8_t bin;
    uint8_t resvd1;
};
 
struct switchtec_gen5_diag_eye_read_out {
    uint8_t num_phases;
    uint8_t resvd1[3];
    uint32_t resvd2;
    uint64_t ber_data[60];
};
 
enum switchtec_diag_loopback_enable {
    SWITCHTEC_DIAG_LOOPBACK_RX_TO_TX = 1 << 0,
    SWITCHTEC_DIAG_LOOPBACK_TX_TO_RX = 1 << 1,
    SWITCHTEC_DIAG_LOOPBACK_LTSSM = 1 << 2,
};
 
enum switchtec_diag_pattern {
    SWITCHTEC_DIAG_PATTERN_PRBS_7,
    SWITCHTEC_DIAG_PATTERN_PRBS_11,
    SWITCHTEC_DIAG_PATTERN_PRBS_23,
    SWITCHTEC_DIAG_PATTERN_PRBS_31,
    SWITCHTEC_DIAG_PATTERN_PRBS_9,
    SWITCHTEC_DIAG_PATTERN_PRBS_15,
    SWITCHTEC_DIAG_PATTERN_PRBS_DISABLED,
};
 
enum switchtec_diag_pattern_gen5 {
    SWITCHTEC_DIAG_GEN_5_PATTERN_PRBS_7,
    SWITCHTEC_DIAG_GEN_5_PATTERN_PRBS_11,
    SWITCHTEC_DIAG_GEN_5_PATTERN_PRBS_23,
    SWITCHTEC_DIAG_GEN_5_PATTERN_PRBS_31,
    SWITCHTEC_DIAG_GEN_5_PATTERN_PRBS_9,
    SWITCHTEC_DIAG_GEN_5_PATTERN_PRBS_15,
    SWITCHTEC_DIAG_GEN_5_PATTERN_PRBS_5,
    SWITCHTEC_DIAG_GEN_5_PATTERN_PRBS_20,
    SWITCHTEC_DIAG_GEN_5_RESERVED_0,
    SWITCHTEC_DIAG_GEN_5_RESERVED_1,
    SWITCHTEC_DIAG_GEN_5_PATTERN_PRBS_DISABLED,
};
 
enum switchtec_diag_pattern_link_rate {
    SWITCHTEC_DIAG_PAT_LINK_DISABLED = 0,
    SWITCHTEC_DIAG_PAT_LINK_GEN1 = 1,
    SWITCHTEC_DIAG_PAT_LINK_GEN2 = 2,
    SWITCHTEC_DIAG_PAT_LINK_GEN3 = 3,
    SWITCHTEC_DIAG_PAT_LINK_GEN4 = 4,
    SWITCHTEC_DIAG_PAT_LINK_GEN5 = 5,
};
 
enum switchtec_diag_ltssm_speed {
    SWITCHTEC_DIAG_LTSSM_GEN1 = 0,
    SWITCHTEC_DIAG_LTSSM_GEN2 = 1,
    SWITCHTEC_DIAG_LTSSM_GEN3 = 2,
    SWITCHTEC_DIAG_LTSSM_GEN4 = 3,
    SWITCHTEC_DIAG_LTSSM_GEN5 = 4,
};
 
enum switchtec_diag_end {
    SWITCHTEC_DIAG_LOCAL,
    SWITCHTEC_DIAG_FAR_END,
};
 
enum switchtec_diag_link {
    SWITCHTEC_DIAG_LINK_CURRENT,
    SWITCHTEC_DIAG_LINK_PREVIOUS,
};
 
enum switchtec_gen5_diag_eye_status {
    SWITCHTEC_GEN5_DIAG_EYE_STATUS_IDLE = 0,
    SWITCHTEC_GEN5_DIAG_EYE_STATUS_PENDING = 1,
    SWITCHTEC_GEN5_DIAG_EYE_STATUS_IN_PROGRESS = 2,
    SWITCHTEC_GEN5_DIAG_EYE_STATUS_DONE = 3,
    SWITCHTEC_GEN5_DIAG_EYE_STATUS_TIMEOUT = 4,
    SWITCHTEC_GEN5_DIAG_EYE_STATUS_ERROR = 5,
};
 
struct switchtec_diag_ltssm_log {
    unsigned int timestamp;
    float link_rate;
    int link_state;
};
 
int switchtec_diag_cross_hair_enable(struct switchtec_dev *dev, int lane_id);
int switchtec_diag_cross_hair_disable(struct switchtec_dev *dev);
int switchtec_diag_cross_hair_get(struct switchtec_dev *dev, int start_lane_id,
        int num_lanes, struct switchtec_diag_cross_hair *res);
 
int switchtec_diag_eye_set_mode(struct switchtec_dev *dev,
                enum switchtec_diag_eye_data_mode mode);
int switchtec_diag_eye_read(struct switchtec_dev *dev, int lane_id, int bin, 
                    int* num_phases, double* ber_data);
int switchtec_diag_eye_start(struct switchtec_dev *dev, int lane_mask[4],
                 struct range *x_range, struct range *y_range,
                 int step_interval, int capture_depth);
int switchtec_diag_eye_fetch(struct switchtec_dev *dev, double *pixels,
                 size_t pixel_cnt, int *lane_id);
int switchtec_diag_eye_cancel(struct switchtec_dev *dev);
 
int switchtec_diag_loopback_set(struct switchtec_dev *dev, int port_id, 
                int enable, int enable_parallel, 
                int enable_external, int enable_ltssm,
                enum switchtec_diag_ltssm_speed ltssm_speed);
int switchtec_diag_loopback_get(struct switchtec_dev *dev, int port_id,
                int *enabled, 
                enum switchtec_diag_ltssm_speed *ltssm_speed);
int switchtec_diag_pattern_gen_set(struct switchtec_dev *dev, int port_id,
                   enum switchtec_diag_pattern type,
                   enum switchtec_diag_pattern_link_rate 
                   link_speed);
int switchtec_diag_pattern_gen_get(struct switchtec_dev *dev, int port_id,
                   enum switchtec_diag_pattern *type);
int switchtec_diag_pattern_mon_set(struct switchtec_dev *dev, int port_id,
                   enum switchtec_diag_pattern type);
int switchtec_diag_pattern_mon_get(struct switchtec_dev *dev, int port_id,
                   int lane_id, 
                   enum switchtec_diag_pattern *type,
                   unsigned long long *err_cnt);
int switchtec_diag_pattern_inject(struct switchtec_dev *dev, int port_id,
                  unsigned int err_cnt);
 
int switchtec_diag_rcvr_obj(struct switchtec_dev *dev, int port_id,
        int lane_id, enum switchtec_diag_link link,
        struct switchtec_rcvr_obj *res);
int switchtec_diag_rcvr_ext(struct switchtec_dev *dev, int port_id,
                int lane_id, enum switchtec_diag_link link,
                struct switchtec_rcvr_ext *res);
 
int switchtec_diag_port_eq_tx_coeff(struct switchtec_dev *dev, int port_id, 
                    int prev_speed, enum switchtec_diag_end end, 
                    enum switchtec_diag_link link,
                    struct switchtec_port_eq_coeff *res);
int switchtec_diag_port_eq_tx_table(struct switchtec_dev *dev, int port_id, 
                    int prev_speed, 
                    enum switchtec_diag_link link,
                    struct switchtec_port_eq_table *res);
int switchtec_diag_port_eq_tx_fslf(struct switchtec_dev *dev, int port_id, 
                   int prev_speed, int lane_id, 
                   enum switchtec_diag_end end,
                   enum switchtec_diag_link link,
                   struct switchtec_port_eq_tx_fslf *res);
 
int switchtec_diag_perm_table(struct switchtec_dev *dev,
                  struct switchtec_mrpc table[MRPC_MAX_ID]);
int switchtec_diag_refclk_ctl(struct switchtec_dev *dev, int stack_id, bool en);
int switchtec_diag_refclk_status(struct switchtec_dev *dev, uint8_t *stack_info);
int switchtec_diag_ltssm_clear(struct switchtec_dev *dev, int port);
int switchtec_diag_ltssm_log(struct switchtec_dev *dev,
                 int port, int *log_count,
                 struct switchtec_diag_ltssm_log *log_data);
int switchtec_tlp_inject(struct switchtec_dev * dev, int port_id, int tlp_type, 
             int tlp_length, int ecrc, uint32_t * raw_tlp_data);
int switchtec_aer_event_gen(struct switchtec_dev *dev, int port_id,
                int aer_error_id, int trigger_event);
int switchtec_osa(struct switchtec_dev * dev, int stack_id, int operation);
int switchtec_osa_config_type(struct switchtec_dev * dev, int stack_id, 
                  int direction, int lane_mask, int link_rate, 
                  int os_types);
int switchtec_osa_config_misc(struct switchtec_dev * dev, int stack_id, 
                  int trigger_en);
int switchtec_osa_capture_control(struct switchtec_dev * dev, int stack_id, 
                  int lane_mask, int direction, 
                  int drop_single_os, int stop_mode,
                  int snapshot_mode, int post_trigger, 
                  int os_types);
int switchtec_osa_dump_conf(struct switchtec_dev * dev, int stack_id);
int switchtec_osa_config_pattern(struct switchtec_dev * dev, int stack_id, 
                 int direction, int lane_mask,int link_rate, 
                 uint32_t * value_data, uint32_t * mask_data);
int switchtec_osa_capture_data(struct switchtec_dev * dev, int stack_id, 
                   int lane, int direction);
#ifdef __cplusplus
}
#endif
 
#endif